2102 Static RAM Lab
07/29/2001
Purpose
To be able to understand the basic addressing, timing, and Data Input-Output (I/O) Relationships, in Addressing Memories, in their relationship to other possible circuitry -- especially CPU's.
Extended Philosophy
Since every computer system in existence uses the basic concepts presented in this project, it is important for the participant to glean all that he/she can from this lab.
This Completed Circuit should be able to
- Access any Memory Address (within a 4-bit boundary), by a single switch keystroke ("EXAMINE"), and then automatically retrieve and Display the contents of memory at that address as 4 Data-Bits, by a signal called "MREAD".
- Sequence to the next memory address, by a single switch keystroke ("EXAMINE NEXT"), and then as before: automatically retrieve and Display the contents of memory at that address as 4 Data-Bits.
- Capture 4 parallel data values as "LSB" through "MSB", by a single switch keystroke ("DEPOSIT"), writing them into memory at that location by a signal called "MWRITE", and also Display those 4 Data-Bits as a result of the OUTPUT of memory. Memory Address should not change.
- Sequencing to next Memory Address, and then Deposit, by "DEPOSIT NEXT", is an option.
- Decrementing back to the previous Memory Address, by "EXAMINE LAST", is an option.
Other Circuit Requirements are
- A delay of ~ 1 micro-second ("MWAIT") for Address Settling Time, before either "MREAD" or "MWRITE" is made active.
- The "MWRITE Strobe" is to be mot more than ~1 micro-second for each individual data bit as it is written into memory.
- Data Bits are to be written into memory, or read from memory, at a 1 Khz rate (i.e. 1 ms spacing).
- All address lines are to monitored (displayed) by LED's,
grouped as either 8x2, or 2x8.
[ LED Drivers required ] - The 8 Address Lines are considered as the "Principle" Address, and the 2 Address Lines may be considered as either "Quadrant" or as "Sequential" Address Lines, so as to appear as a 256x4 SRAM.
- The Data Monitors will display the data from memory, whether it be a result of an "EXAMINE" or "DEPOSIT". (i.e. execute a "MREAD after "MWRITE", or during "MWRITE").
Timing Diagram Illustration for this Lab
Test Procedure
- Set the Address Switches (or wires) for the desired address,
and then execute "EXAMINE" to assess memory by "MWAIT"
and "MREAD".
- Correct address should be indicated on the address LED's.
- The 4 Data-Values from memory contents should appear in the Data-Monitor LED's.
- "EXAMINE NEXT" should cause auto-step to the next location in memory (indicated by the Address Monitor LED's), and the respective 4-Bit Data for that "Principle" Address should also appear.
- Set the 4 Data-Switches for a Data-Input, and activate "DEPOSIT".
- The Data-Values are to written into memory, with no address change.
- The Data-Values should automatically be displayed as the output of memory, not from the circuit that writes into memory.
Breadboarding Circuit for implementing this lab.
Note
The normal method of writing into the next memory location, would be by "EXAMINE NEXT", and then "DEPOSIT", but an option in addition to that method would be to simply do "DEPOSIT NEXT" with an appropriate circuit.